Generally, cells of a semiconductor device are laid out according to a place-and-route boundary (prBoundary). For example, a first cell is abutted against a second cell along prBoundaries for the respective cells. However, a prBoundary is not flexible, and placement of cells is not efficient in some scenarios when cells are placed or abutted according to a prBoundary. For example, such cell placement is associated with a decrease in power, performance, and area (PPA). Moreover, prBoundary cell placement wastes space in some scenarios at least because the first cell is separated from the second cell by decap cells or filler cells.